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<== Date ==> <== Thread ==>

Subject: Re: Newport XPS-Q8 and Motor Record - armv5teb architecture
From: Torsten Bögershausen <torsten.bogershausen@esss.se>
To: "Johnson, Andrew N." <anj@aps.anl.gov>, "Rivers, Mark L." <rivers@cars.uchicago.edu>
Cc: "tech-talk@aps.anl.gov" <tech-talk@aps.anl.gov>, Tonia Batten <Tonia.Batten@lightsource.ca>
Date: Thu, 8 May 2014 08:13:42 +0200


On 5/7/14 11:32 PM, Johnson, Andrew N. wrote:
Hi Mark,

You could try adding a call to the gcc built-in routine __sync_synchronize(); after the last write to the asynUser structure. This implements a full memory barrier, which is equivalent to the two memory barriers inside the mutex operations. If this fixes it for ARM there is probably a better solution, but this will at least identify if this is the cause of the problem.

This would be needed on a multi-core system.

What system is in use ?
single core or multi core?

I just got the motor simulator working on the Raspberry PI, (after some days of debugging)
The trick was to use this block in motorApp/MotorSrc/motor.h:

==============
/* Define, from top to bottom, how bit fields are packed. */
/* This works for gnu, SunPro, MS Visual C. */
#include <epicsEndian.h>
#if (EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE)
    #define LSB_First (TRUE)
    #warning LSB_First
#endif

#if (EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG)
    #define MSB_First (TRUE)
    #warning MSB_First
#endif


===============

What do you get when you compile with this change ? MSB_First or LSB_First ?




Replies:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Tonia Batten
References:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture J. Lewis Muir
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Stephen Beckwith
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Stephen Beckwith
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Jens Eden
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture J. Lewis Muir
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Johnson, Andrew N.
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Johnson, Andrew N.

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